\doxysection{Class List}
Here are the classes, structs, unions and interfaces with brief descriptions\+:\begin{DoxyCompactList}
\item\contentsline{section}{\mbox{\hyperlink{struct__}{\+\_\+}} }{\pageref{struct__}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_____d_m_a___handle_type_def}{\+\_\+\+\_\+\+DMA\+\_\+\+Handle\+Type\+Def}} \\*DMA handle Structure definition }{\pageref{struct_____d_m_a___handle_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_____i2_c___handle_type_def}{\+\_\+\+\_\+\+I2\+C\+\_\+\+Handle\+Type\+Def}} }{\pageref{struct_____i2_c___handle_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct____iar__u32}{\+\_\+\+\_\+iar\+\_\+u32}} }{\pageref{struct____iar__u32}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_____m_d_m_a___handle_type_def}{\+\_\+\+\_\+\+MDMA\+\_\+\+Handle\+Type\+Def}} \\*MDMA handle Structure definition }{\pageref{struct_____m_d_m_a___handle_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_____s_p_i___handle_type_def}{\+\_\+\+\_\+\+SPI\+\_\+\+Handle\+Type\+Def}} \\*SPI handle Structure definition }{\pageref{struct_____s_p_i___handle_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_____u_a_r_t___handle_type_def}{\+\_\+\+\_\+\+UART\+\_\+\+Handle\+Type\+Def}} \\*UART handle Structure definition }{\pageref{struct_____u_a_r_t___handle_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_a___b_l_o_c_k___l_i_n_k}{A\+\_\+\+BLOCK\+\_\+\+LINK}} }{\pageref{struct_a___b_l_o_c_k___l_i_n_k}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_a_d_c___common___type_def}{ADC\+\_\+\+Common\+\_\+\+Type\+Def}} }{\pageref{struct_a_d_c___common___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_a_d_c___type_def}{ADC\+\_\+\+Type\+Def}} \\*Analog to Digital Converter }{\pageref{struct_a_d_c___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{union_a_p_s_r___type}{APSR\+\_\+\+Type}} \\*Union type to access the Application Program Status Register (APSR) }{\pageref{union_a_p_s_r___type}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__bilinear__interp__instance__f32}{arm\+\_\+bilinear\+\_\+interp\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point bilinear interpolation function }{\pageref{structarm__bilinear__interp__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__bilinear__interp__instance__q15}{arm\+\_\+bilinear\+\_\+interp\+\_\+instance\+\_\+q15}} \\*Instance structure for the Q15 bilinear interpolation function }{\pageref{structarm__bilinear__interp__instance__q15}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__bilinear__interp__instance__q31}{arm\+\_\+bilinear\+\_\+interp\+\_\+instance\+\_\+q31}} \\*Instance structure for the Q31 bilinear interpolation function }{\pageref{structarm__bilinear__interp__instance__q31}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__bilinear__interp__instance__q7}{arm\+\_\+bilinear\+\_\+interp\+\_\+instance\+\_\+q7}} \\*Instance structure for the Q15 bilinear interpolation function }{\pageref{structarm__bilinear__interp__instance__q7}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__biquad__cas__df1__32x64__ins__q31}{arm\+\_\+biquad\+\_\+cas\+\_\+df1\+\_\+32x64\+\_\+ins\+\_\+q31}} \\*Instance structure for the high precision Q31 Biquad cascade filter }{\pageref{structarm__biquad__cas__df1__32x64__ins__q31}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__biquad__cascade__df2_t__instance__f32}{arm\+\_\+biquad\+\_\+cascade\+\_\+df2\+T\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point transposed direct form II Biquad cascade filter }{\pageref{structarm__biquad__cascade__df2_t__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__biquad__cascade__df2_t__instance__f64}{arm\+\_\+biquad\+\_\+cascade\+\_\+df2\+T\+\_\+instance\+\_\+f64}} \\*Instance structure for the floating-\/point transposed direct form II Biquad cascade filter }{\pageref{structarm__biquad__cascade__df2_t__instance__f64}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__biquad__cascade__stereo__df2_t__instance__f32}{arm\+\_\+biquad\+\_\+cascade\+\_\+stereo\+\_\+df2\+T\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point transposed direct form II Biquad cascade filter }{\pageref{structarm__biquad__cascade__stereo__df2_t__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__biquad__casd__df1__inst__f32}{arm\+\_\+biquad\+\_\+casd\+\_\+df1\+\_\+inst\+\_\+f32}} \\*Instance structure for the floating-\/point Biquad cascade filter }{\pageref{structarm__biquad__casd__df1__inst__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__biquad__casd__df1__inst__q15}{arm\+\_\+biquad\+\_\+casd\+\_\+df1\+\_\+inst\+\_\+q15}} \\*Instance structure for the Q15 Biquad cascade filter }{\pageref{structarm__biquad__casd__df1__inst__q15}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__biquad__casd__df1__inst__q31}{arm\+\_\+biquad\+\_\+casd\+\_\+df1\+\_\+inst\+\_\+q31}} \\*Instance structure for the Q31 Biquad cascade filter }{\pageref{structarm__biquad__casd__df1__inst__q31}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__cfft__instance__f32}{arm\+\_\+cfft\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point CFFT/\+CIFFT function }{\pageref{structarm__cfft__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__cfft__instance__f64}{arm\+\_\+cfft\+\_\+instance\+\_\+f64}} \\*Instance structure for the Double Precision Floating-\/point CFFT/\+CIFFT function }{\pageref{structarm__cfft__instance__f64}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__cfft__instance__q15}{arm\+\_\+cfft\+\_\+instance\+\_\+q15}} \\*Instance structure for the fixed-\/point CFFT/\+CIFFT function }{\pageref{structarm__cfft__instance__q15}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__cfft__instance__q31}{arm\+\_\+cfft\+\_\+instance\+\_\+q31}} \\*Instance structure for the fixed-\/point CFFT/\+CIFFT function }{\pageref{structarm__cfft__instance__q31}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__cfft__radix2__instance__f32}{arm\+\_\+cfft\+\_\+radix2\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point CFFT/\+CIFFT function }{\pageref{structarm__cfft__radix2__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__cfft__radix2__instance__q15}{arm\+\_\+cfft\+\_\+radix2\+\_\+instance\+\_\+q15}} \\*Instance structure for the Q15 CFFT/\+CIFFT function }{\pageref{structarm__cfft__radix2__instance__q15}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__cfft__radix2__instance__q31}{arm\+\_\+cfft\+\_\+radix2\+\_\+instance\+\_\+q31}} \\*Instance structure for the Radix-\/2 Q31 CFFT/\+CIFFT function }{\pageref{structarm__cfft__radix2__instance__q31}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__cfft__radix4__instance__f32}{arm\+\_\+cfft\+\_\+radix4\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point CFFT/\+CIFFT function }{\pageref{structarm__cfft__radix4__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__cfft__radix4__instance__q15}{arm\+\_\+cfft\+\_\+radix4\+\_\+instance\+\_\+q15}} \\*Instance structure for the Q15 CFFT/\+CIFFT function }{\pageref{structarm__cfft__radix4__instance__q15}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__cfft__radix4__instance__q31}{arm\+\_\+cfft\+\_\+radix4\+\_\+instance\+\_\+q31}} \\*Instance structure for the Q31 CFFT/\+CIFFT function }{\pageref{structarm__cfft__radix4__instance__q31}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__dct4__instance__f32}{arm\+\_\+dct4\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point DCT4/\+IDCT4 function }{\pageref{structarm__dct4__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__dct4__instance__q15}{arm\+\_\+dct4\+\_\+instance\+\_\+q15}} \\*Instance structure for the Q15 DCT4/\+IDCT4 function }{\pageref{structarm__dct4__instance__q15}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__dct4__instance__q31}{arm\+\_\+dct4\+\_\+instance\+\_\+q31}} \\*Instance structure for the Q31 DCT4/\+IDCT4 function }{\pageref{structarm__dct4__instance__q31}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__fir__decimate__instance__f32}{arm\+\_\+fir\+\_\+decimate\+\_\+instance\+\_\+f32}} \\*Instance structure for floating-\/point FIR decimator }{\pageref{structarm__fir__decimate__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__fir__decimate__instance__q15}{arm\+\_\+fir\+\_\+decimate\+\_\+instance\+\_\+q15}} \\*Instance structure for the Q15 FIR decimator }{\pageref{structarm__fir__decimate__instance__q15}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__fir__decimate__instance__q31}{arm\+\_\+fir\+\_\+decimate\+\_\+instance\+\_\+q31}} \\*Instance structure for the Q31 FIR decimator }{\pageref{structarm__fir__decimate__instance__q31}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__fir__instance__f32}{arm\+\_\+fir\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point FIR filter }{\pageref{structarm__fir__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__fir__instance__f64}{arm\+\_\+fir\+\_\+instance\+\_\+f64}} \\*Instance structure for the floating-\/point FIR filter }{\pageref{structarm__fir__instance__f64}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__fir__instance__q15}{arm\+\_\+fir\+\_\+instance\+\_\+q15}} \\*Instance structure for the Q15 FIR filter }{\pageref{structarm__fir__instance__q15}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__fir__instance__q31}{arm\+\_\+fir\+\_\+instance\+\_\+q31}} \\*Instance structure for the Q31 FIR filter }{\pageref{structarm__fir__instance__q31}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__fir__instance__q7}{arm\+\_\+fir\+\_\+instance\+\_\+q7}} \\*Instance structure for the Q7 FIR filter }{\pageref{structarm__fir__instance__q7}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__fir__interpolate__instance__f32}{arm\+\_\+fir\+\_\+interpolate\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point FIR interpolator }{\pageref{structarm__fir__interpolate__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__fir__interpolate__instance__q15}{arm\+\_\+fir\+\_\+interpolate\+\_\+instance\+\_\+q15}} \\*Instance structure for the Q15 FIR interpolator }{\pageref{structarm__fir__interpolate__instance__q15}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__fir__interpolate__instance__q31}{arm\+\_\+fir\+\_\+interpolate\+\_\+instance\+\_\+q31}} \\*Instance structure for the Q31 FIR interpolator }{\pageref{structarm__fir__interpolate__instance__q31}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__fir__lattice__instance__f32}{arm\+\_\+fir\+\_\+lattice\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point FIR lattice filter }{\pageref{structarm__fir__lattice__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__fir__lattice__instance__q15}{arm\+\_\+fir\+\_\+lattice\+\_\+instance\+\_\+q15}} \\*Instance structure for the Q15 FIR lattice filter }{\pageref{structarm__fir__lattice__instance__q15}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__fir__lattice__instance__q31}{arm\+\_\+fir\+\_\+lattice\+\_\+instance\+\_\+q31}} \\*Instance structure for the Q31 FIR lattice filter }{\pageref{structarm__fir__lattice__instance__q31}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__fir__sparse__instance__f32}{arm\+\_\+fir\+\_\+sparse\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point sparse FIR filter }{\pageref{structarm__fir__sparse__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__fir__sparse__instance__q15}{arm\+\_\+fir\+\_\+sparse\+\_\+instance\+\_\+q15}} \\*Instance structure for the Q15 sparse FIR filter }{\pageref{structarm__fir__sparse__instance__q15}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__fir__sparse__instance__q31}{arm\+\_\+fir\+\_\+sparse\+\_\+instance\+\_\+q31}} \\*Instance structure for the Q31 sparse FIR filter }{\pageref{structarm__fir__sparse__instance__q31}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__fir__sparse__instance__q7}{arm\+\_\+fir\+\_\+sparse\+\_\+instance\+\_\+q7}} \\*Instance structure for the Q7 sparse FIR filter }{\pageref{structarm__fir__sparse__instance__q7}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__gaussian__naive__bayes__instance__f32}{arm\+\_\+gaussian\+\_\+naive\+\_\+bayes\+\_\+instance\+\_\+f32}} \\*Instance structure for Naive Gaussian Bayesian estimator }{\pageref{structarm__gaussian__naive__bayes__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__iir__lattice__instance__f32}{arm\+\_\+iir\+\_\+lattice\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point IIR lattice filter }{\pageref{structarm__iir__lattice__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__iir__lattice__instance__q15}{arm\+\_\+iir\+\_\+lattice\+\_\+instance\+\_\+q15}} \\*Instance structure for the Q15 IIR lattice filter }{\pageref{structarm__iir__lattice__instance__q15}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__iir__lattice__instance__q31}{arm\+\_\+iir\+\_\+lattice\+\_\+instance\+\_\+q31}} \\*Instance structure for the Q31 IIR lattice filter }{\pageref{structarm__iir__lattice__instance__q31}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__linear__interp__instance__f32}{arm\+\_\+linear\+\_\+interp\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point Linear Interpolate function }{\pageref{structarm__linear__interp__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__lms__instance__f32}{arm\+\_\+lms\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point LMS filter }{\pageref{structarm__lms__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__lms__instance__q15}{arm\+\_\+lms\+\_\+instance\+\_\+q15}} \\*Instance structure for the Q15 LMS filter }{\pageref{structarm__lms__instance__q15}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__lms__instance__q31}{arm\+\_\+lms\+\_\+instance\+\_\+q31}} \\*Instance structure for the Q31 LMS filter }{\pageref{structarm__lms__instance__q31}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__lms__norm__instance__f32}{arm\+\_\+lms\+\_\+norm\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point normalized LMS filter }{\pageref{structarm__lms__norm__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__lms__norm__instance__q15}{arm\+\_\+lms\+\_\+norm\+\_\+instance\+\_\+q15}} \\*Instance structure for the Q15 normalized LMS filter }{\pageref{structarm__lms__norm__instance__q15}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__lms__norm__instance__q31}{arm\+\_\+lms\+\_\+norm\+\_\+instance\+\_\+q31}} \\*Instance structure for the Q31 normalized LMS filter }{\pageref{structarm__lms__norm__instance__q31}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__matrix__instance__f32}{arm\+\_\+matrix\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point matrix structure }{\pageref{structarm__matrix__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__matrix__instance__f64}{arm\+\_\+matrix\+\_\+instance\+\_\+f64}} \\*Instance structure for the floating-\/point matrix structure }{\pageref{structarm__matrix__instance__f64}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__matrix__instance__q15}{arm\+\_\+matrix\+\_\+instance\+\_\+q15}} \\*Instance structure for the Q15 matrix structure }{\pageref{structarm__matrix__instance__q15}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__matrix__instance__q31}{arm\+\_\+matrix\+\_\+instance\+\_\+q31}} \\*Instance structure for the Q31 matrix structure }{\pageref{structarm__matrix__instance__q31}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__matrix__instance__q7}{arm\+\_\+matrix\+\_\+instance\+\_\+q7}} \\*Instance structure for the Q7 matrix structure }{\pageref{structarm__matrix__instance__q7}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__merge__sort__instance__f32}{arm\+\_\+merge\+\_\+sort\+\_\+instance\+\_\+f32}} \\*Instance structure for the sorting algorithms }{\pageref{structarm__merge__sort__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__mfcc__instance__f32}{arm\+\_\+mfcc\+\_\+instance\+\_\+f32}} \\*Instance structure for the Floating-\/point MFCC function }{\pageref{structarm__mfcc__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__mfcc__instance__q15}{arm\+\_\+mfcc\+\_\+instance\+\_\+q15}} }{\pageref{structarm__mfcc__instance__q15}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__mfcc__instance__q31}{arm\+\_\+mfcc\+\_\+instance\+\_\+q31}} }{\pageref{structarm__mfcc__instance__q31}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_a_r_m___m_p_u___region__t}{ARM\+\_\+\+MPU\+\_\+\+Region\+\_\+t}} }{\pageref{struct_a_r_m___m_p_u___region__t}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__pid__instance__f32}{arm\+\_\+pid\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point PID Control }{\pageref{structarm__pid__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__pid__instance__q15}{arm\+\_\+pid\+\_\+instance\+\_\+q15}} \\*Instance structure for the Q15 PID Control }{\pageref{structarm__pid__instance__q15}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__pid__instance__q31}{arm\+\_\+pid\+\_\+instance\+\_\+q31}} \\*Instance structure for the Q31 PID Control }{\pageref{structarm__pid__instance__q31}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__rfft__fast__instance__f32}{arm\+\_\+rfft\+\_\+fast\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point RFFT/\+RIFFT function }{\pageref{structarm__rfft__fast__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__rfft__fast__instance__f64}{arm\+\_\+rfft\+\_\+fast\+\_\+instance\+\_\+f64}} \\*Instance structure for the Double Precision Floating-\/point RFFT/\+RIFFT function }{\pageref{structarm__rfft__fast__instance__f64}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__rfft__instance__f32}{arm\+\_\+rfft\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point RFFT/\+RIFFT function }{\pageref{structarm__rfft__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__rfft__instance__q15}{arm\+\_\+rfft\+\_\+instance\+\_\+q15}} \\*Instance structure for the Q15 RFFT/\+RIFFT function }{\pageref{structarm__rfft__instance__q15}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__rfft__instance__q31}{arm\+\_\+rfft\+\_\+instance\+\_\+q31}} \\*Instance structure for the Q31 RFFT/\+RIFFT function }{\pageref{structarm__rfft__instance__q31}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__sort__instance__f32}{arm\+\_\+sort\+\_\+instance\+\_\+f32}} \\*Instance structure for the sorting algorithms }{\pageref{structarm__sort__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__spline__instance__f32}{arm\+\_\+spline\+\_\+instance\+\_\+f32}} \\*Instance structure for the floating-\/point cubic spline interpolation }{\pageref{structarm__spline__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__svm__linear__instance__f32}{arm\+\_\+svm\+\_\+linear\+\_\+instance\+\_\+f32}} \\*Instance structure for linear SVM prediction function }{\pageref{structarm__svm__linear__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__svm__polynomial__instance__f32}{arm\+\_\+svm\+\_\+polynomial\+\_\+instance\+\_\+f32}} \\*Instance structure for polynomial SVM prediction function }{\pageref{structarm__svm__polynomial__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__svm__rbf__instance__f32}{arm\+\_\+svm\+\_\+rbf\+\_\+instance\+\_\+f32}} \\*Instance structure for rbf SVM prediction function }{\pageref{structarm__svm__rbf__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structarm__svm__sigmoid__instance__f32}{arm\+\_\+svm\+\_\+sigmoid\+\_\+instance\+\_\+f32}} \\*Instance structure for sigmoid SVM prediction function }{\pageref{structarm__svm__sigmoid__instance__f32}}{}
\item\contentsline{section}{\mbox{\hyperlink{structattitude__t}{attitude\+\_\+t}} }{\pageref{structattitude__t}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_b_d_m_a___channel___type_def}{BDMA\+\_\+\+Channel\+\_\+\+Type\+Def}} }{\pageref{struct_b_d_m_a___channel___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_b_d_m_a___type_def}{BDMA\+\_\+\+Type\+Def}} }{\pageref{struct_b_d_m_a___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_callback_task__t}{Callback\+Task\+\_\+t}} }{\pageref{struct_callback_task__t}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_c_a_n___init___config__s}{CAN\+\_\+\+Init\+\_\+\+Config\+\_\+s}} }{\pageref{struct_c_a_n___init___config__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_c_a_n_comm___init___config__s}{CANComm\+\_\+\+Init\+\_\+\+Config\+\_\+s}} }{\pageref{struct_c_a_n_comm___init___config__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_c_a_n_comm_instance}{CANComm\+Instance}} }{\pageref{struct_c_a_n_comm_instance}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_c_e_c___type_def}{CEC\+\_\+\+Type\+Def}} \\*Consumer Electronics Control }{\pageref{struct_c_e_c___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_c_o_m_p___common___type_def}{COMP\+\_\+\+Common\+\_\+\+Type\+Def}} }{\pageref{struct_c_o_m_p___common___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_c_o_m_p___type_def}{COMP\+\_\+\+Type\+Def}} }{\pageref{struct_c_o_m_p___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_c_o_m_p_o_p_t___type_def}{COMPOPT\+\_\+\+Type\+Def}} \\*Comparator }{\pageref{struct_c_o_m_p_o_p_t___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{union_c_o_n_t_r_o_l___type}{CONTROL\+\_\+\+Type}} \\*Union type to access the Control Registers (CONTROL) }{\pageref{union_c_o_n_t_r_o_l___type}}{}
\item\contentsline{section}{\mbox{\hyperlink{structcor_co_routine_control_block}{cor\+Co\+Routine\+Control\+Block}} }{\pageref{structcor_co_routine_control_block}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_c_o_r_d_i_c___type_def}{CORDIC\+\_\+\+Type\+Def}} \\*COordincate Rotation DIgital Computer }{\pageref{struct_c_o_r_d_i_c___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_core_debug___type}{Core\+Debug\+\_\+\+Type}} \\*Structure type to access the Core Debug Register (Core\+Debug) }{\pageref{struct_core_debug___type}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_c_r_c___type_def}{CRC\+\_\+\+Type\+Def}} \\*CRC calculation unit }{\pageref{struct_c_r_c___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_c_r_s___type_def}{CRS\+\_\+\+Type\+Def}} \\*Clock Recovery System }{\pageref{struct_c_r_s___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_a_c___type_def}{DAC\+\_\+\+Type\+Def}} \\*Digital to Analog Converter }{\pageref{struct_d_a_c___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_daemon___init___config__s}{Daemon\+\_\+\+Init\+\_\+\+Config\+\_\+s}} }{\pageref{struct_daemon___init___config__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{structdaemon__ins}{daemon\+\_\+ins}} }{\pageref{structdaemon__ins}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_b_g_m_c_u___type_def}{DBGMCU\+\_\+\+Type\+Def}} \\*Debug MCU }{\pageref{struct_d_b_g_m_c_u___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_c_m_i___type_def}{DCMI\+\_\+\+Type\+Def}} \\*DCMI }{\pageref{struct_d_c_m_i___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_f_s_d_m___channel___type_def}{DFSDM\+\_\+\+Channel\+\_\+\+Type\+Def}} \\*DFSDM channel configuration registers }{\pageref{struct_d_f_s_d_m___channel___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_f_s_d_m___filter___type_def}{DFSDM\+\_\+\+Filter\+\_\+\+Type\+Def}} \\*DFSDM module registers }{\pageref{struct_d_f_s_d_m___filter___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_j_i___motor___measure__s}{DJI\+\_\+\+Motor\+\_\+\+Measure\+\_\+s}} }{\pageref{struct_d_j_i___motor___measure__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_j_i_motor_instance}{DJIMotor\+Instance}} \\*DJI intelligent motor typedef }{\pageref{struct_d_j_i_motor_instance}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_l_y_b___type_def}{DLYB\+\_\+\+Type\+Def}} \\*Delay Block DLYB }{\pageref{struct_d_l_y_b___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_m___motor___measure__s}{DM\+\_\+\+Motor\+\_\+\+Measure\+\_\+s}} }{\pageref{struct_d_m___motor___measure__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_m_a2_d___type_def}{DMA2\+D\+\_\+\+Type\+Def}} \\*DMA2D Controller }{\pageref{struct_d_m_a2_d___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_m_a___init_type_def}{DMA\+\_\+\+Init\+Type\+Def}} \\*DMA Configuration Structure definition }{\pageref{struct_d_m_a___init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\+\_\+\+Stream\+\_\+\+Type\+Def}} \\*DMA Controller }{\pageref{struct_d_m_a___stream___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\+\_\+\+Type\+Def}} }{\pageref{struct_d_m_a___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_m_a_m_u_x___channel___type_def}{DMAMUX\+\_\+\+Channel\+\_\+\+Type\+Def}} }{\pageref{struct_d_m_a_m_u_x___channel___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_m_a_m_u_x___channel_status___type_def}{DMAMUX\+\_\+\+Channel\+Status\+\_\+\+Type\+Def}} }{\pageref{struct_d_m_a_m_u_x___channel_status___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_m_a_m_u_x___request_gen___type_def}{DMAMUX\+\_\+\+Request\+Gen\+\_\+\+Type\+Def}} }{\pageref{struct_d_m_a_m_u_x___request_gen___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_m_a_m_u_x___request_gen_status___type_def}{DMAMUX\+\_\+\+Request\+Gen\+Status\+\_\+\+Type\+Def}} }{\pageref{struct_d_m_a_m_u_x___request_gen_status___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_m_motor___send__s}{DMMotor\+\_\+\+Send\+\_\+s}} }{\pageref{struct_d_m_motor___send__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_m_motor_instance}{DMMotor\+Instance}} }{\pageref{struct_d_m_motor_instance}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_t_s___type_def}{DTS\+\_\+\+Type\+Def}} \\*DTS }{\pageref{struct_d_t_s___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_w_t___time__t}{DWT\+\_\+\+Time\+\_\+t}} }{\pageref{struct_d_w_t___time__t}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_d_w_t___type}{DWT\+\_\+\+Type}} \\*Structure type to access the Data Watchpoint and Trace Register (DWT) }{\pageref{struct_d_w_t___type}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_e_t_h___type_def}{ETH\+\_\+\+Type\+Def}} \\*Ethernet MAC }{\pageref{struct_e_t_h___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_event_group_def__t}{Event\+Group\+Def\+\_\+t}} }{\pageref{struct_event_group_def__t}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_e_x_t_i___config_type_def}{EXTI\+\_\+\+Config\+Type\+Def}} \\*EXTI Configuration structure definition }{\pageref{struct_e_x_t_i___config_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_e_x_t_i___core___type_def}{EXTI\+\_\+\+Core\+\_\+\+Type\+Def}} \\*This structure registers corresponds to EXTI\+\_\+\+Typdef CPU1/\+CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI\+\_\+\+D1/\+EXTI\+\_\+\+D2 with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. Note that EXTI\+\_\+\+D1 and EXTI\+\_\+\+D2 bases addresses are calculated to point to CPUx first register\+: IMR1 in case of EXTI\+\_\+\+D1 that is addressing CPU1 (Cortex-\/\+M7) C2\+IMR1 in case of EXTI\+\_\+\+D2 that is addressing CPU2 (Cortex-\/\+M4) Note\+: EXTI\+\_\+\+D2 and corresponding C2\+IMRx, C2\+EMRx and C2\+PRx registers are available for Dual Core devices only }{\pageref{struct_e_x_t_i___core___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_e_x_t_i___handle_type_def}{EXTI\+\_\+\+Handle\+Type\+Def}} \\*EXTI Handle structure definition }{\pageref{struct_e_x_t_i___handle_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_e_x_t_i___type_def}{EXTI\+\_\+\+Type\+Def}} \\*External Interrupt/\+Event Controller }{\pageref{struct_e_x_t_i___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_f_d_c_a_n___clock_calibration_unit___type_def}{FDCAN\+\_\+\+Clock\+Calibration\+Unit\+\_\+\+Type\+Def}} \\*FD Controller Area Network }{\pageref{struct_f_d_c_a_n___clock_calibration_unit___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_f_d_c_a_n___global_type_def}{FDCAN\+\_\+\+Global\+Type\+Def}} \\*FD Controller Area Network }{\pageref{struct_f_d_c_a_n___global_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_f_l_a_s_h___c_r_c_init_type_def}{FLASH\+\_\+\+CRCInit\+Type\+Def}} \\*FLASH Erase structure definition }{\pageref{struct_f_l_a_s_h___c_r_c_init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_f_l_a_s_h___erase_init_type_def}{FLASH\+\_\+\+Erase\+Init\+Type\+Def}} \\*FLASH Erase structure definition }{\pageref{struct_f_l_a_s_h___erase_init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_f_l_a_s_h___o_b_program_init_type_def}{FLASH\+\_\+\+OBProgram\+Init\+Type\+Def}} \\*FLASH Option Bytes Program structure definition }{\pageref{struct_f_l_a_s_h___o_b_program_init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_f_l_a_s_h___process_type_def}{FLASH\+\_\+\+Process\+Type\+Def}} \\*FLASH handle Structure definition }{\pageref{struct_f_l_a_s_h___process_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_f_l_a_s_h___type_def}{FLASH\+\_\+\+Type\+Def}} \\*FLASH Registers }{\pageref{struct_f_l_a_s_h___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_f_m_a_c___type_def}{FMAC\+\_\+\+Type\+Def}} \\*Filter and Mathematical ACcelerator }{\pageref{struct_f_m_a_c___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_f_m_c___bank1___type_def}{FMC\+\_\+\+Bank1\+\_\+\+Type\+Def}} \\*Flexible Memory Controller }{\pageref{struct_f_m_c___bank1___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_f_m_c___bank1_e___type_def}{FMC\+\_\+\+Bank1\+E\+\_\+\+Type\+Def}} \\*Flexible Memory Controller Bank1E }{\pageref{struct_f_m_c___bank1_e___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_f_m_c___bank2___type_def}{FMC\+\_\+\+Bank2\+\_\+\+Type\+Def}} \\*Flexible Memory Controller Bank2 }{\pageref{struct_f_m_c___bank2___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_f_m_c___bank3___type_def}{FMC\+\_\+\+Bank3\+\_\+\+Type\+Def}} \\*Flexible Memory Controller Bank3 }{\pageref{struct_f_m_c___bank3___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_f_m_c___bank5__6___type_def}{FMC\+\_\+\+Bank5\+\_\+6\+\_\+\+Type\+Def}} \\*Flexible Memory Controller Bank5 and 6 }{\pageref{struct_f_m_c___bank5__6___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_f_p_u___type}{FPU\+\_\+\+Type}} \\*Structure type to access the Floating Point Unit (FPU) }{\pageref{struct_f_p_u___type}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_g_p_i_o___init___config__s}{GPIO\+\_\+\+Init\+\_\+\+Config\+\_\+s}} \\*GPIO初始化配置结构体定义 }{\pageref{struct_g_p_i_o___init___config__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_g_p_i_o___init_type_def}{GPIO\+\_\+\+Init\+Type\+Def}} \\*GPIO Init structure definition }{\pageref{struct_g_p_i_o___init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_g_p_i_o___type_def}{GPIO\+\_\+\+Type\+Def}} \\*General Purpose I/O }{\pageref{struct_g_p_i_o___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_g_p_v___type_def}{GPV\+\_\+\+Type\+Def}} \\*Global Programmer View }{\pageref{struct_g_p_v___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_h_a_l___d_m_a___mux_request_generator_config_type_def}{HAL\+\_\+\+DMA\+\_\+\+Mux\+Request\+Generator\+Config\+Type\+Def}} \\*HAL DMAMUX request generator parameters structure definition }{\pageref{struct_h_a_l___d_m_a___mux_request_generator_config_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_h_a_l___d_m_a___mux_sync_config_type_def}{HAL\+\_\+\+DMA\+\_\+\+Mux\+Sync\+Config\+Type\+Def}} \\*HAL DMAMUX Synchronization configuration structure definition }{\pageref{struct_h_a_l___d_m_a___mux_sync_config_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_heap_region}{Heap\+Region}} }{\pageref{struct_heap_region}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_h_s_e_m___common___type_def}{HSEM\+\_\+\+Common\+\_\+\+Type\+Def}} }{\pageref{struct_h_s_e_m___common___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_h_s_e_m___type_def}{HSEM\+\_\+\+Type\+Def}} \\*HW Semaphore HSEM }{\pageref{struct_h_s_e_m___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_h_t_motor___measure__t}{HTMotor\+\_\+\+Measure\+\_\+t}} }{\pageref{struct_h_t_motor___measure__t}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_h_t_motor_instance}{HTMotor\+Instance}} }{\pageref{struct_h_t_motor_instance}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_i2_c___init_type_def}{I2\+C\+\_\+\+Init\+Type\+Def}} }{\pageref{struct_i2_c___init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_i2_c___type_def}{I2\+C\+\_\+\+Type\+Def}} \\*Inter-\/integrated Circuit Interface }{\pageref{struct_i2_c___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_i_i_c___init___config__s}{IIC\+\_\+\+Init\+\_\+\+Config\+\_\+s}} }{\pageref{struct_i_i_c___init___config__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{structiic__temp__s}{iic\+\_\+temp\+\_\+s}} }{\pageref{structiic__temp__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_i_m_u___data__t}{IMU\+\_\+\+Data\+\_\+t}} }{\pageref{struct_i_m_u___data__t}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_i_m_u___param__t}{IMU\+\_\+\+Param\+\_\+t}} }{\pageref{struct_i_m_u___param__t}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_i_n_s__t}{INS\+\_\+t}} }{\pageref{struct_i_n_s__t}}{}
\item\contentsline{section}{\mbox{\hyperlink{union_i_p_s_r___type}{IPSR\+\_\+\+Type}} \\*Union type to access the Interrupt Program Status Register (IPSR) }{\pageref{union_i_p_s_r___type}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_i_t_m___type}{ITM\+\_\+\+Type}} \\*Structure type to access the Instrumentation Trace Macrocell Register (ITM) }{\pageref{struct_i_t_m___type}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_i_w_d_g___type_def}{IWDG\+\_\+\+Type\+Def}} \\*Independent WATCHDOG }{\pageref{struct_i_w_d_g___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{union_key__t}{Key\+\_\+t}} }{\pageref{union_key__t}}{}
\item\contentsline{section}{\mbox{\hyperlink{structkf__t}{kf\+\_\+t}} }{\pageref{structkf__t}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_l_k_motor___measure__t}{LKMotor\+\_\+\+Measure\+\_\+t}} }{\pageref{struct_l_k_motor___measure__t}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_l_k_motor_instance}{LKMotor\+Instance}} }{\pageref{struct_l_k_motor_instance}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_l_l___u_t_i_l_s___clk_init_type_def}{LL\+\_\+\+UTILS\+\_\+\+Clk\+Init\+Type\+Def}} \\*UTILS System, AHB and APB buses clock configuration structure definition }{\pageref{struct_l_l___u_t_i_l_s___clk_init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_l_l___u_t_i_l_s___p_l_l_init_type_def}{LL\+\_\+\+UTILS\+\_\+\+PLLInit\+Type\+Def}} \\*UTILS PLL structure definition }{\pageref{struct_l_l___u_t_i_l_s___p_l_l_init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_l_p_t_i_m___type_def}{LPTIM\+\_\+\+Type\+Def}} \\*LPTIMIMER }{\pageref{struct_l_p_t_i_m___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_l_t_d_c___layer___type_def}{LTDC\+\_\+\+Layer\+\_\+\+Type\+Def}} \\*LCD-\/\+TFT Display layer x Controller }{\pageref{struct_l_t_d_c___layer___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_l_t_d_c___type_def}{LTDC\+\_\+\+Type\+Def}} \\*LCD-\/\+TFT Display Controller }{\pageref{struct_l_t_d_c___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_m_d_i_o_s___type_def}{MDIOS\+\_\+\+Type\+Def}} \\*MDIOS }{\pageref{struct_m_d_i_o_s___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_m_d_m_a___channel___type_def}{MDMA\+\_\+\+Channel\+\_\+\+Type\+Def}} }{\pageref{struct_m_d_m_a___channel___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_m_d_m_a___init_type_def}{MDMA\+\_\+\+Init\+Type\+Def}} \\*MDMA Configuration Structure definition }{\pageref{struct_m_d_m_a___init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_m_d_m_a___link_node_conf_type_def}{MDMA\+\_\+\+Link\+Node\+Conf\+Type\+Def}} \\*HAL MDMA linked list node configuration structure definition }{\pageref{struct_m_d_m_a___link_node_conf_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_m_d_m_a___link_node_type_def}{MDMA\+\_\+\+Link\+Node\+Type\+Def}} \\*HAL MDMA linked list node structure definition }{\pageref{struct_m_d_m_a___link_node_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_m_d_m_a___type_def}{MDMA\+\_\+\+Type\+Def}} \\*MDMA Controller }{\pageref{struct_m_d_m_a___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_motor___control___setting__s}{Motor\+\_\+\+Control\+\_\+\+Setting\+\_\+s}} }{\pageref{struct_motor___control___setting__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_motor___controller___init__s}{Motor\+\_\+\+Controller\+\_\+\+Init\+\_\+s}} \\*电机控制器初始化结构体,包括三环\+PID的配置以及两个反馈数据来源指针 如果不需要某个控制环,可以不设置对应的pid config 需要其他数据来源进行反馈闭环,不仅要设置这里的指针还需要在\+Motor\+\_\+\+Control\+\_\+\+Setting\+\_\+s启用其他数据来源标志 }{\pageref{struct_motor___controller___init__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_motor___controller__s}{Motor\+\_\+\+Controller\+\_\+s}} }{\pageref{struct_motor___controller__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_motor___init___config__s}{Motor\+\_\+\+Init\+\_\+\+Config\+\_\+s}} }{\pageref{struct_motor___init___config__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_m_p_u___type}{MPU\+\_\+\+Type}} \\*Structure type to access the Memory Protection Unit (MPU) }{\pageref{struct_m_p_u___type}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_n_v_i_c___type}{NVIC\+\_\+\+Type}} \\*Structure type to access the Nested Vectored Interrupt Controller (NVIC) }{\pageref{struct_n_v_i_c___type}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def}{OCTOSPI\+\_\+\+Type\+Def}} \\*OCTO Serial Peripheral Interface }{\pageref{struct_o_c_t_o_s_p_i___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_o_c_t_o_s_p_i_m___type_def}{OCTOSPIM\+\_\+\+Type\+Def}} \\*OCTO Serial Peripheral Interface IO Manager }{\pageref{struct_o_c_t_o_s_p_i_m___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_o_p_a_m_p___type_def}{OPAMP\+\_\+\+Type\+Def}} \\*Operational Amplifier (OPAMP) }{\pageref{struct_o_p_a_m_p___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{structos__mail_q__cb}{os\+\_\+mail\+Q\+\_\+cb}} }{\pageref{structos__mail_q__cb}}{}
\item\contentsline{section}{\mbox{\hyperlink{structos__mail_q__def}{os\+\_\+mail\+Q\+\_\+def}} }{\pageref{structos__mail_q__def}}{}
\item\contentsline{section}{\mbox{\hyperlink{structos__message_q__def}{os\+\_\+message\+Q\+\_\+def}} }{\pageref{structos__message_q__def}}{}
\item\contentsline{section}{\mbox{\hyperlink{structos__mutex__def}{os\+\_\+mutex\+\_\+def}} }{\pageref{structos__mutex__def}}{}
\item\contentsline{section}{\mbox{\hyperlink{structos__pool__cb}{os\+\_\+pool\+\_\+cb}} }{\pageref{structos__pool__cb}}{}
\item\contentsline{section}{\mbox{\hyperlink{structos__pool__def}{os\+\_\+pool\+\_\+def}} }{\pageref{structos__pool__def}}{}
\item\contentsline{section}{\mbox{\hyperlink{structos__semaphore__def}{os\+\_\+semaphore\+\_\+def}} }{\pageref{structos__semaphore__def}}{}
\item\contentsline{section}{\mbox{\hyperlink{structos__thread__def}{os\+\_\+thread\+\_\+def}} }{\pageref{structos__thread__def}}{}
\item\contentsline{section}{\mbox{\hyperlink{structos__timer__def}{os\+\_\+timer\+\_\+def}} }{\pageref{structos__timer__def}}{}
\item\contentsline{section}{\mbox{\hyperlink{structos_event}{os\+Event}} }{\pageref{structos_event}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_p_i_d___error_handler__t}{PID\+\_\+\+Error\+Handler\+\_\+t}} }{\pageref{struct_p_i_d___error_handler__t}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_p_i_d___init___config__s}{PID\+\_\+\+Init\+\_\+\+Config\+\_\+s}} }{\pageref{struct_p_i_d___init___config__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_p_i_d_instance}{PIDInstance}} }{\pageref{struct_p_i_d_instance}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_p_l_l1___clocks_type_def}{PLL1\+\_\+\+Clocks\+Type\+Def}} \\*RCC PLL1 Clocks structure definition }{\pageref{struct_p_l_l1___clocks_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_p_l_l2___clocks_type_def}{PLL2\+\_\+\+Clocks\+Type\+Def}} \\*RCC PLL2 Clocks structure definition }{\pageref{struct_p_l_l2___clocks_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_p_l_l3___clocks_type_def}{PLL3\+\_\+\+Clocks\+Type\+Def}} \\*RCC PLL3 Clocks structure definition }{\pageref{struct_p_l_l3___clocks_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{structprotocol__rm__struct}{protocol\+\_\+rm\+\_\+struct}} }{\pageref{structprotocol__rm__struct}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_p_s_s_i___type_def}{PSSI\+\_\+\+Type\+Def}} \\*PSSI }{\pageref{struct_p_s_s_i___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_p_w_m___init___config__s}{PWM\+\_\+\+Init\+\_\+\+Config\+\_\+s}} }{\pageref{struct_p_w_m___init___config__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{structpwm__ins__temp}{pwm\+\_\+ins\+\_\+temp}} }{\pageref{structpwm__ins__temp}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_p_w_r___p_v_d_type_def}{PWR\+\_\+\+PVDType\+Def}} \\*PWR PVD configuration structure definition }{\pageref{struct_p_w_r___p_v_d_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_p_w_r___type_def}{PWR\+\_\+\+Type\+Def}} \\*Power Control }{\pageref{struct_p_w_r___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_p_w_r_ex___a_v_d_type_def}{PWREx\+\_\+\+AVDType\+Def}} \\*PWREx AVD configuration structure definition }{\pageref{struct_p_w_r_ex___a_v_d_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_p_w_r_ex___wakeup_pin_type_def}{PWREx\+\_\+\+Wakeup\+Pin\+Type\+Def}} \\*PWREx Wakeup pin configuration structure definition }{\pageref{struct_p_w_r_ex___wakeup_pin_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_q_e_k_f___i_n_s__t}{QEKF\+\_\+\+INS\+\_\+t}} }{\pageref{struct_q_e_k_f___i_n_s__t}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_queue_definition}{Queue\+Definition}} }{\pageref{struct_queue_definition}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_queue_pointers}{Queue\+Pointers}} }{\pageref{struct_queue_pointers}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_r_a_m_e_c_c___monitor_type_def}{RAMECC\+\_\+\+Monitor\+Type\+Def}} \\*RAM\+\_\+\+ECC\+\_\+\+Specific\+\_\+\+Registers }{\pageref{struct_r_a_m_e_c_c___monitor_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_r_a_m_e_c_c___type_def}{RAMECC\+\_\+\+Type\+Def}} }{\pageref{struct_r_a_m_e_c_c___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_r_c__ctrl__t}{RC\+\_\+ctrl\+\_\+t}} }{\pageref{struct_r_c__ctrl__t}}{}
\item\contentsline{section}{\mbox{\hyperlink{structrc__ctrl__t}{rc\+\_\+ctrl\+\_\+t}} }{\pageref{structrc__ctrl__t}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_r_c_c___clk_init_type_def}{RCC\+\_\+\+Clk\+Init\+Type\+Def}} \\*RCC System, AHB and APB busses clock configuration structure definition }{\pageref{struct_r_c_c___clk_init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_r_c_c___c_r_s_init_type_def}{RCC\+\_\+\+CRSInit\+Type\+Def}} \\*RCC\+\_\+\+CRS Init structure definition }{\pageref{struct_r_c_c___c_r_s_init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_r_c_c___c_r_s_synchro_info_type_def}{RCC\+\_\+\+CRSSynchro\+Info\+Type\+Def}} \\*RCC\+\_\+\+CRS Synchronization structure definition }{\pageref{struct_r_c_c___c_r_s_synchro_info_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_r_c_c___osc_init_type_def}{RCC\+\_\+\+Osc\+Init\+Type\+Def}} \\*RCC Internal/\+External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition }{\pageref{struct_r_c_c___osc_init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_r_c_c___periph_c_l_k_init_type_def}{RCC\+\_\+\+Periph\+CLKInit\+Type\+Def}} \\*RCC extended clocks structure definition }{\pageref{struct_r_c_c___periph_c_l_k_init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_r_c_c___p_l_l2_init_type_def}{RCC\+\_\+\+PLL2\+Init\+Type\+Def}} \\*PLL2 Clock structure definition }{\pageref{struct_r_c_c___p_l_l2_init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_r_c_c___p_l_l3_init_type_def}{RCC\+\_\+\+PLL3\+Init\+Type\+Def}} \\*PLL3 Clock structure definition }{\pageref{struct_r_c_c___p_l_l3_init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_r_c_c___p_l_l_init_type_def}{RCC\+\_\+\+PLLInit\+Type\+Def}} \\*RCC PLL configuration structure definition }{\pageref{struct_r_c_c___p_l_l_init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_r_c_c___type_def}{RCC\+\_\+\+Type\+Def}} \\*Reset and Clock Control }{\pageref{struct_r_c_c___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{structremoter__t}{remoter\+\_\+t}} }{\pageref{structremoter__t}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_r_n_g___type_def}{RNG\+\_\+\+Type\+Def}} \\*RNG }{\pageref{struct_r_n_g___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_r_t_c___type_def}{RTC\+\_\+\+Type\+Def}} \\*Real-\/\+Time Clock }{\pageref{struct_r_t_c___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_a_i___block___type_def}{SAI\+\_\+\+Block\+\_\+\+Type\+Def}} }{\pageref{struct_s_a_i___block___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_a_i___type_def}{SAI\+\_\+\+Type\+Def}} \\*Serial Audio Interface }{\pageref{struct_s_a_i___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_c_b___type}{SCB\+\_\+\+Type}} \\*Structure type to access the System Control Block (SCB) }{\pageref{struct_s_c_b___type}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_cn_s_c_b___type}{SCn\+SCB\+\_\+\+Type}} \\*Structure type to access the System Control and ID Register not in the SCB }{\pageref{struct_s_cn_s_c_b___type}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_d_m_m_c___type_def}{SDMMC\+\_\+\+Type\+Def}} \\*Secure digital input/output Interface }{\pageref{struct_s_d_m_m_c___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_e_g_g_e_r___b_s_p___a_p_i}{SEGGER\+\_\+\+BSP\+\_\+\+API}} }{\pageref{struct_s_e_g_g_e_r___b_s_p___a_p_i}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_e_g_g_e_r___b_u_f_f_e_r___d_e_s_c}{SEGGER\+\_\+\+BUFFER\+\_\+\+DESC}} }{\pageref{struct_s_e_g_g_e_r___b_u_f_f_e_r___d_e_s_c}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_e_g_g_e_r___c_a_c_h_e___c_o_n_f_i_g}{SEGGER\+\_\+\+CACHE\+\_\+\+CONFIG}} }{\pageref{struct_s_e_g_g_e_r___c_a_c_h_e___c_o_n_f_i_g}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_e_g_g_e_r___p_r_i_n_t_f___a_p_i}{SEGGER\+\_\+\+PRINTF\+\_\+\+API}} }{\pageref{struct_s_e_g_g_e_r___p_r_i_n_t_f___a_p_i}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_e_g_g_e_r___p_r_i_n_t_f___f_o_r_m_a_t_t_e_r}{SEGGER\+\_\+\+PRINTF\+\_\+\+FORMATTER}} }{\pageref{struct_s_e_g_g_e_r___p_r_i_n_t_f___f_o_r_m_a_t_t_e_r}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_e_g_g_e_r___r_t_t___b_u_f_f_e_r___d_o_w_n}{SEGGER\+\_\+\+RTT\+\_\+\+BUFFER\+\_\+\+DOWN}} }{\pageref{struct_s_e_g_g_e_r___r_t_t___b_u_f_f_e_r___d_o_w_n}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_e_g_g_e_r___r_t_t___b_u_f_f_e_r___u_p}{SEGGER\+\_\+\+RTT\+\_\+\+BUFFER\+\_\+\+UP}} }{\pageref{struct_s_e_g_g_e_r___r_t_t___b_u_f_f_e_r___u_p}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_e_g_g_e_r___r_t_t___c_b}{SEGGER\+\_\+\+RTT\+\_\+\+CB}} }{\pageref{struct_s_e_g_g_e_r___r_t_t___c_b}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_e_g_g_e_r___r_t_t___p_r_i_n_t_f___d_e_s_c}{SEGGER\+\_\+\+RTT\+\_\+\+PRINTF\+\_\+\+DESC}} }{\pageref{struct_s_e_g_g_e_r___r_t_t___p_r_i_n_t_f___d_e_s_c}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_e_g_g_e_r___s_n_p_r_i_n_t_f___c_o_n_t_e_x_t__struct}{SEGGER\+\_\+\+SNPRINTF\+\_\+\+CONTEXT\+\_\+struct}} }{\pageref{struct_s_e_g_g_e_r___s_n_p_r_i_n_t_f___c_o_n_t_e_x_t__struct}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_e_g_g_e_r___s_y_s_v_i_e_w___g_l_o_b_a_l_s}{SEGGER\+\_\+\+SYSVIEW\+\_\+\+GLOBALS}} }{\pageref{struct_s_e_g_g_e_r___s_y_s_v_i_e_w___g_l_o_b_a_l_s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_e_g_g_e_r___s_y_s_v_i_e_w___m_o_d_u_l_e___s_t_r_u_c_t}{SEGGER\+\_\+\+SYSVIEW\+\_\+\+MODULE\+\_\+\+STRUCT}} }{\pageref{struct_s_e_g_g_e_r___s_y_s_v_i_e_w___m_o_d_u_l_e___s_t_r_u_c_t}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_e_g_g_e_r___s_y_s_v_i_e_w___o_s___a_p_i}{SEGGER\+\_\+\+SYSVIEW\+\_\+\+OS\+\_\+\+API}} }{\pageref{struct_s_e_g_g_e_r___s_y_s_v_i_e_w___o_s___a_p_i}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_e_g_g_e_r___s_y_s_v_i_e_w___p_r_i_n_t_f___d_e_s_c}{SEGGER\+\_\+\+SYSVIEW\+\_\+\+PRINTF\+\_\+\+DESC}} }{\pageref{struct_s_e_g_g_e_r___s_y_s_v_i_e_w___p_r_i_n_t_f___d_e_s_c}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_e_g_g_e_r___s_y_s_v_i_e_w___t_a_s_k_i_n_f_o}{SEGGER\+\_\+\+SYSVIEW\+\_\+\+TASKINFO}} }{\pageref{struct_s_e_g_g_e_r___s_y_s_v_i_e_w___t_a_s_k_i_n_f_o}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_semaphore_data}{Semaphore\+Data}} }{\pageref{struct_semaphore_data}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_servo___angle__s}{Servo\+\_\+\+Angle\+\_\+s}} }{\pageref{struct_servo___angle__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_servo___init___config__s}{Servo\+\_\+\+Init\+\_\+\+Config\+\_\+s}} }{\pageref{struct_servo___init___config__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_servo_instance}{Servo\+Instance}} }{\pageref{struct_servo_instance}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_p_d_i_f_r_x___type_def}{SPDIFRX\+\_\+\+Type\+Def}} \\*SPDIF-\/\+RX Interface }{\pageref{struct_s_p_d_i_f_r_x___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_p_i___init___config__s}{SPI\+\_\+\+Init\+\_\+\+Config\+\_\+s}} }{\pageref{struct_s_p_i___init___config__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_p_i___init_type_def}{SPI\+\_\+\+Init\+Type\+Def}} \\*SPI Configuration Structure definition }{\pageref{struct_s_p_i___init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{structspi__ins__temp}{spi\+\_\+ins\+\_\+temp}} }{\pageref{structspi__ins__temp}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\+\_\+\+Type\+Def}} \\*Serial Peripheral Interface }{\pageref{struct_s_p_i___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_stream_buffer_def__t}{Stream\+Buffer\+Def\+\_\+t}} }{\pageref{struct_stream_buffer_def__t}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_w_p_m_i___type_def}{SWPMI\+\_\+\+Type\+Def}} \\*Single Wire Protocol Master Interface SPWMI }{\pageref{struct_s_w_p_m_i___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_y_s_c_f_g___type_def}{SYSCFG\+\_\+\+Type\+Def}} \\*System configuration controller }{\pageref{struct_s_y_s_c_f_g___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_sys_tick___type}{Sys\+Tick\+\_\+\+Type}} \\*Structure type to access the System Timer (Sys\+Tick) }{\pageref{struct_sys_tick___type}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_s_y_s_v_i_e_w___f_r_e_e_r_t_o_s___t_a_s_k___s_t_a_t_u_s}{SYSVIEW\+\_\+\+FREERTOS\+\_\+\+TASK\+\_\+\+STATUS}} }{\pageref{struct_s_y_s_v_i_e_w___f_r_e_e_r_t_o_s___t_a_s_k___s_t_a_t_u_s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_t_i_m___base___init_type_def}{TIM\+\_\+\+Base\+\_\+\+Init\+Type\+Def}} \\*TIM Time base Configuration Structure definition }{\pageref{struct_t_i_m___base___init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_t_i_m___break_dead_time_config_type_def}{TIM\+\_\+\+Break\+Dead\+Time\+Config\+Type\+Def}} \\*TIM Break input(s) and Dead time configuration Structure definition }{\pageref{struct_t_i_m___break_dead_time_config_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_t_i_m___clear_input_config_type_def}{TIM\+\_\+\+Clear\+Input\+Config\+Type\+Def}} \\*TIM Clear Input Configuration Handle Structure definition }{\pageref{struct_t_i_m___clear_input_config_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_t_i_m___clock_config_type_def}{TIM\+\_\+\+Clock\+Config\+Type\+Def}} \\*Clock Configuration Handle Structure definition }{\pageref{struct_t_i_m___clock_config_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_t_i_m___encoder___init_type_def}{TIM\+\_\+\+Encoder\+\_\+\+Init\+Type\+Def}} \\*TIM Encoder Configuration Structure definition }{\pageref{struct_t_i_m___encoder___init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_t_i_m___hall_sensor___init_type_def}{TIM\+\_\+\+Hall\+Sensor\+\_\+\+Init\+Type\+Def}} \\*TIM Hall sensor Configuration Structure definition }{\pageref{struct_t_i_m___hall_sensor___init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\+\_\+\+Handle\+Type\+Def}} \\*TIM Time Base Handle Structure definition }{\pageref{struct_t_i_m___handle_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_t_i_m___i_c___init_type_def}{TIM\+\_\+\+IC\+\_\+\+Init\+Type\+Def}} \\*TIM Input Capture Configuration Structure definition }{\pageref{struct_t_i_m___i_c___init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_t_i_m___master_config_type_def}{TIM\+\_\+\+Master\+Config\+Type\+Def}} \\*TIM Master configuration Structure definition }{\pageref{struct_t_i_m___master_config_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_t_i_m___o_c___init_type_def}{TIM\+\_\+\+OC\+\_\+\+Init\+Type\+Def}} \\*TIM Output Compare Configuration Structure definition }{\pageref{struct_t_i_m___o_c___init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_t_i_m___one_pulse___init_type_def}{TIM\+\_\+\+One\+Pulse\+\_\+\+Init\+Type\+Def}} \\*TIM One Pulse Mode Configuration Structure definition }{\pageref{struct_t_i_m___one_pulse___init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_t_i_m___slave_config_type_def}{TIM\+\_\+\+Slave\+Config\+Type\+Def}} \\*TIM Slave configuration Structure definition }{\pageref{struct_t_i_m___slave_config_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\+\_\+\+Type\+Def}} \\*TIM }{\pageref{struct_t_i_m___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{structtmpgpio}{tmpgpio}} \\*GPIO实例结构体定义 }{\pageref{structtmpgpio}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_t_p_i___type}{TPI\+\_\+\+Type}} \\*Structure type to access the Trace Port Interface Register (TPI) }{\pageref{struct_t_p_i___type}}{}
\item\contentsline{section}{\mbox{\hyperlink{structtsk_task_control_block}{tsk\+Task\+Control\+Block}} }{\pageref{structtsk_task_control_block}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_t_t_c_a_n___type_def}{TTCAN\+\_\+\+Type\+Def}} \\*TTFD Controller Area Network }{\pageref{struct_t_t_c_a_n___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_u_a_r_t___adv_feature_init_type_def}{UART\+\_\+\+Adv\+Feature\+Init\+Type\+Def}} \\*UART Advanced Features initialization structure definition }{\pageref{struct_u_a_r_t___adv_feature_init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_u_a_r_t___init_type_def}{UART\+\_\+\+Init\+Type\+Def}} \\*UART Init Structure definition }{\pageref{struct_u_a_r_t___init_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_u_a_r_t___wake_up_type_def}{UART\+\_\+\+Wake\+Up\+Type\+Def}} \\*UART wake up from stop mode parameters }{\pageref{struct_u_a_r_t___wake_up_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_u_s_a_r_t___init___config__s}{USART\+\_\+\+Init\+\_\+\+Config\+\_\+s}} }{\pageref{struct_u_s_a_r_t___init___config__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_u_s_a_r_t___type_def}{USART\+\_\+\+Type\+Def}} \\*Universal Synchronous Asynchronous Receiver Transmitter }{\pageref{struct_u_s_a_r_t___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_u_s_a_r_t_instance}{USARTInstance}} }{\pageref{struct_u_s_a_r_t_instance}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_u_s_b___init___config__s}{USB\+\_\+\+Init\+\_\+\+Config\+\_\+s}} }{\pageref{struct_u_s_b___init___config__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_u_s_b___o_t_g___device_type_def}{USB\+\_\+\+OTG\+\_\+\+Device\+Type\+Def}} \\*USB\+\_\+\+OTG\+\_\+device\+\_\+\+Registers }{\pageref{struct_u_s_b___o_t_g___device_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_u_s_b___o_t_g___global_type_def}{USB\+\_\+\+OTG\+\_\+\+Global\+Type\+Def}} \\*USB\+\_\+\+OTG\+\_\+\+Core\+\_\+\+Registers }{\pageref{struct_u_s_b___o_t_g___global_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_u_s_b___o_t_g___host_channel_type_def}{USB\+\_\+\+OTG\+\_\+\+Host\+Channel\+Type\+Def}} \\*USB\+\_\+\+OTG\+\_\+\+Host\+\_\+\+Channel\+\_\+\+Specific\+\_\+\+Registers }{\pageref{struct_u_s_b___o_t_g___host_channel_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_u_s_b___o_t_g___host_type_def}{USB\+\_\+\+OTG\+\_\+\+Host\+Type\+Def}} \\*USB\+\_\+\+OTG\+\_\+\+Host\+\_\+\+Mode\+\_\+\+Register\+\_\+\+Structures }{\pageref{struct_u_s_b___o_t_g___host_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_u_s_b___o_t_g___i_n_endpoint_type_def}{USB\+\_\+\+OTG\+\_\+\+INEndpoint\+Type\+Def}} \\*USB\+\_\+\+OTG\+\_\+\+IN\+\_\+\+Endpoint-\/\+Specific\+\_\+\+Register }{\pageref{struct_u_s_b___o_t_g___i_n_endpoint_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_u_s_b___o_t_g___o_u_t_endpoint_type_def}{USB\+\_\+\+OTG\+\_\+\+OUTEndpoint\+Type\+Def}} \\*USB\+\_\+\+OTG\+\_\+\+OUT\+\_\+\+Endpoint-\/\+Specific\+\_\+\+Registers }{\pageref{struct_u_s_b___o_t_g___o_u_t_endpoint_type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_vision___recv__s}{Vision\+\_\+\+Recv\+\_\+s}} }{\pageref{struct_vision___recv__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_vision___send__s}{Vision\+\_\+\+Send\+\_\+s}} }{\pageref{struct_vision___send__s}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_v_r_e_f_b_u_f___type_def}{VREFBUF\+\_\+\+Type\+Def}} \\*VREFBUF }{\pageref{struct_v_r_e_f_b_u_f___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct_w_w_d_g___type_def}{WWDG\+\_\+\+Type\+Def}} \\*Window WATCHDOG }{\pageref{struct_w_w_d_g___type_def}}{}
\item\contentsline{section}{\mbox{\hyperlink{structx_heap_stats}{x\+Heap\+Stats}} }{\pageref{structx_heap_stats}}{}
\item\contentsline{section}{\mbox{\hyperlink{structx_l_i_s_t}{x\+LIST}} }{\pageref{structx_l_i_s_t}}{}
\item\contentsline{section}{\mbox{\hyperlink{structx_l_i_s_t___i_t_e_m}{x\+LIST\+\_\+\+ITEM}} }{\pageref{structx_l_i_s_t___i_t_e_m}}{}
\item\contentsline{section}{\mbox{\hyperlink{structx_m_e_m_o_r_y___r_e_g_i_o_n}{x\+MEMORY\+\_\+\+REGION}} }{\pageref{structx_m_e_m_o_r_y___r_e_g_i_o_n}}{}
\item\contentsline{section}{\mbox{\hyperlink{structx_m_i_n_i___l_i_s_t___i_t_e_m}{x\+MINI\+\_\+\+LIST\+\_\+\+ITEM}} }{\pageref{structx_m_i_n_i___l_i_s_t___i_t_e_m}}{}
\item\contentsline{section}{\mbox{\hyperlink{unionx_p_s_r___type}{x\+PSR\+\_\+\+Type}} \\*Union type to access the Special-\/\+Purpose Program Status Registers (x\+PSR) }{\pageref{unionx_p_s_r___type}}{}
\item\contentsline{section}{\mbox{\hyperlink{structx_s_t_a_t_i_c___e_v_e_n_t___g_r_o_u_p}{x\+STATIC\+\_\+\+EVENT\+\_\+\+GROUP}} }{\pageref{structx_s_t_a_t_i_c___e_v_e_n_t___g_r_o_u_p}}{}
\item\contentsline{section}{\mbox{\hyperlink{structx_s_t_a_t_i_c___l_i_s_t}{x\+STATIC\+\_\+\+LIST}} }{\pageref{structx_s_t_a_t_i_c___l_i_s_t}}{}
\item\contentsline{section}{\mbox{\hyperlink{structx_s_t_a_t_i_c___l_i_s_t___i_t_e_m}{x\+STATIC\+\_\+\+LIST\+\_\+\+ITEM}} }{\pageref{structx_s_t_a_t_i_c___l_i_s_t___i_t_e_m}}{}
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